|VDD3P3||3||Power Amplifier (Balun)|
|VDD3P3||4||Power Amplifier (Stage 1)|
|VDDPST||11,17||I/O Power Rail|
|VDDD||29||Crystal and PLL Rail|
Pins 3 and 4 are the big power draw rails; the datasheet says up to 300mA may be drawn at peak. Earlier schematics (for the dev board) show that pin 29 and 30 are isolated from each other and are supplied by a common quiet regulator (each has a 47nH and 100nF filter to the regulator). The LNA supply (pin 1) is powered from the same supply as the power amplifier pins (3,4) but is isolated from it with a 50 ohm resistor and a 100nF capacitor. The I/O rail pins (11,17) are connected together and bypassed with 100nF.
The new schematics show everything just pulled together into a common 3.3V rail with 10uF and 100nF capacitors for bypassing.